Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating (or dielectric) layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.
A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET).
Early MOSFET processes used one type of doping to create either positive or negative channel transistors. More recent designs, referred to as complimentary MOS (CMOS) devices, use both positive and negative channel devices, e.g., a positive channel metal oxide semiconductor (PMOS) transistor and a negative channel metal oxide semiconductor (NMOS) transistor, in complimentary configurations. An NMOS device negatively charges so that the transistor is turned on or off by the movement of electrons, whereas a PMOS device involves the movement of electron vacancies. While the manufacture of CMOS devices requires more manufacturing steps and more transistors, CMOS devices are advantageous because they utilize less power, and the devices may be made smaller and faster.
The gate dielectric for MOSFET devices has in the past typically comprised silicon dioxide, which has a dielectric constant of about 3.9. However, as devices are scaled down in size, using silicon dioxide for a gate dielectric becomes a problem because of gate leakage current, which can degrade device performance. For low power logic (for portable electronic applications, for example), it is important to use devices having low leakage current, in order to extend battery life. Gate leakage current must be controlled in low power applications, as well as sub-threshold leakage, junction leakage, and band-to-band tunneling. Therefore, there is a trend in the industry towards the development of the use of high dielectric constant (k) materials for use as the gate dielectric in MOSFET devices, which lowers the gate leakage current. The term “high k dielectric materials” as used herein refers to a dielectric material having a dielectric constant of about 4.0 or greater.
In electronics, the “work function” is the energy, usually measured in electron volts, needed to remove an electron from the Fermi level to a point an infinite distance away outside the surface. Work function is a material property of any material, whether the material is a conductor, semiconductor, or dielectric. The work function of a semiconductor or conductor directly affects the threshold voltage of a transistor when the material is used as a gate electrode. In CMOS devices, it is important that the threshold voltage Vt for the NMOS and PMOS transistors be symmetric, to optimize CMOS device performance.
A problem with using high-k gate dielectric materials such as a hafnium-based dielectric material is that such high-k dielectric materials exhibit a Fermi-pinning effect, which is caused by the interaction of the high-k gate dielectric material with the adjacent gate material. When used as a gate dielectric in a transistor, high k gate dielectric material pins or fixes the work function. The Fermi-pinning effect of high k gate dielectric materials causes a threshold voltage shift and low mobility, due to the increased charge caused by the Fermi-pinning effect. Thus, a symmetric Vt for the NMOS and PMOS transistors of a CMOS device having a high k dielectric material for the gate dielectric is difficult to achieve. Efforts have been made to improve the quality of high-k dielectric films and resolve the Fermi-pinning problems, but the efforts have resulted in little success.
Thus, what are needed in the art are CMOS transistor devices and methods of manufacturing thereof that have a high-k gate dielectric material and a symmetric Vt for the p channel metal oxide semiconductor (PMOS) and n channel metal oxide semiconductor (NMOS) transistors of the CMOS devices.